Many different resistive cross point memory cell arrays have been proposed, including resistive cross point memory cell arrays having MRAM elements, phase change memory elements, resistive polymer memory elements, polysilicon memory elements, and write-once (eg. fuse based or anti-fuse based) resistive memory elements.
Consider the example of an MRAM device including a resistive cross point array of spin dependent tunnelling (SDT) junctions, word lines extending along rows of the SDT junctions, and bit lines extending along columns of the SDT junctions. Each SDT junction is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1’. The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+ΔR) if the magnetization orientation is anti-parallel. The magnetization of the SDT junction and, therefore, its logic value may be read by sensing its resistance state by passing a current through the junction generating a voltage from the magnetic resistance of the cell. Thus the magnetoresistance contains the information on the state of that cell.
A write operation on a selected SDT junction is performed by supplying write currents to the word and bit lines crossing the selected SDT junction. The currents create two external magnetic fields that, when combined, switch the magnetization orientation of the selected SDT junction from parallel to anti-parallel or vice versa.
However, since the junctions are essentially resistors, problems arise in read and write sensitivity as a result of shunt currents passing through junctions other than the selected junction. Such problems are eliminated by placing an electronic switch between the word and bit lines in series with each magnetic cell. Such a device can be a diode or transistor.
A known form of a diode integrated into a magnetic storage element is constructed by building up the various layers of the diode and the magnetic storage element. These layers include p and n layers of the diode followed by the layers of the magnetic storage element including two magnetoresistive layers separated by a non-magnetic layer such as aluminium oxide. Once the required number of layers has been built up, etching takes place to form an array of memory cells each incorporating an integrated diode and magnetic storage element. The diode junction is thus arranged generally parallel with the layers of the magnetic storage element and is also generally parallel with the general plane of the MRAM array.
Another known form of a cross point resistive memory array has memory cells each built on a pillar diode structure. However the equivalent circuit of each memory cell includes a tunnel gate surface effect transistor having non-uniform gate oxide built on the pillar diode structure. Thus, the pillar diode does not function as a diode in the forward conducting direction. Further, the control gate prevents sneak path currents through the memory cell.
It is desirable to resist shunt currents through non-selected junctions of a cross point resistive memory device.